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Failure Analysis

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Failure Analysis

失效分析

Time of issue:2023-01-17 20:02:06

Our product failure analysis has two main purposes:

1.Utilize our professional knowledge and analytical capabilities to develop new products and technologies

2. Preliminary evidence collection analysis of obstacles in continuous quality improvement work and issues reported by customers

Combining the rich experience of the laboratory team, industry standard technology, and internally developed tools, product analysts can identify sub micron level defects from billions of transistors on chip ICs. This approach helps to accurately understand the root cause of faults, quickly take corrective measures, and prevent similar problems from occurring.

 

Product Analysis Process

Step 1- Reproduce the fault in a laboratory environment

Product analysts will use evaluation boards, digital testers and other tools in this Committed step. Special care was taken during this process, such as ESD protection, to ensure that no new defects occurred.

 

Step 2- Packaging Analysis

Using packaging analysis tools and techniques (such as optical inspection, scanning acoustic microscopy, X-ray), first determine whether there are physical defects in the IC packaging around the chip. If defects are found in the packaging, we will explore between the packaging layers to accurately locate the component that caused the fault.

 

Step 3- Defect Space Localization

If there are no defects in the packaging, we remove the device packaging and expose the silicon chip. Localization techniques such as light emission microscopy, thermal detection technology, and diagnostic fault simulation are used to narrow the range of crystal tube sets that may have defects.

 

Step 4- Electrical Analysis

After identifying the problem area, advanced analysis techniques are used to identify individual transistors or components that may cause failure modes. If it is determined that the defect area is on the device packaging, the packaging analyst will explore between the packaging layers to further identify the component causing the failure mode.

 

Step 5- Physical Analysis

We will identify physical defects related to the electrical characteristics of faulty components. This can be achieved by observing each packaging layer under an electron microscope, and if the defect is between the layers, it can be achieved by observing the cross-section.

 

Step 6- Record the analysis results

We will use the results of electrical and physical analysis to identify the fault mechanism and clarify the cause of the fault. Then record the root cause of the fault and complete the product analysis steps. The relevant team will receive the analysis report and immediately take corrective measures.

 

Honor Crowned! Erised Semiconductor Wins "Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industry Pilot Enterprise" Award News 丨 2026-05-09
Under the theme "Innovation · Co-construction of the Chain", the NEX WAVE 2026 Greater Bay Area Strategic Emerging Industries and Future Industries Ecosystem Connectivity Conference was recently held with great ceremony in Shenzhen. The conference was co-hosted by the Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industries Development Promotion Association and the Shenzhen Strategic Emerging Industries Development Promotion Association. More than 500 elites from government, industry, academia, research, finance and other fields gathered to discuss the development of new quality productive forces and industrial ecosystem collaboration. At the conference, Erised Semiconductor (Shenzhen) Co., Ltd., by virtue of its outstanding independent innovation capability and industrial leadership, was awarded the "2025 Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industry Pilot Enterprise" title jointly issued by the Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industries Development Promotion Association and the Shenzhen Strategic Emerging Industries Development Promotion Association! It is reported that this selection campaign officially opened for registration in May 2025 and lasted a total of 8 months. Through steps including "press release, registration, preliminary material review, on-site research, and expert comprehensive evaluation", comprehensive assessments were made across multiple areas such as scientific research, venture capital, industry, and corporate services. In the end, 50 enterprises were selected for the "Pilot Enterprise" list, of which 56% are national-level "Little Giant" specialized and sophisticated enterprises, holding a total of over 17,000 patents. This research is a comprehensive benchmark project initiated by the Strategic Emerging Industries Development Promotion Association in conjunction with several authoritative institutions. It has been held for five consecutive years, cumulatively releasing 250 pilot enterprises, 48 pioneering figures, and 100 young leaders, forming the most influential benchmark ecosystem for strategic emerging industries in the Greater Bay Area. In such a rigorous and authoritative selection, Erised Semiconductor broke through forcefully and, with its outstanding independent innovation capability and industry leadership, was honored on the "Pilot Enterprise" list, adding yet another authoritative accolade in the field of strategic emerging industries. From High-tech Enterprise to Specialized and Sophisticated "Little Giant", and then to Shenzhen Gazelle Enterprise, and now the Greater Bay Area Strategic Emerging Industry "Pilot Enterprise" — every step of Erised Semiconductor's growth has been inseparable from its persistent dedication to technological innovation, and even more so from the trust and support of every customer, partner, and employee. In the future, we will continue to move forward with this honor, contributing irreplaceable "Erised Power" to the high-quality development of the semiconductor industry in the Greater Bay Area with even stronger innovation!

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