Targeting the 800G/1.6T upgrade wave, accelerating the deployment of optical interconnects in AI computing centers with "verifiable, manufacturable, and deliverable" solutions. Erised Semiconductor today announced that it will officially enter the CPO (Co Packaged Optics) field, leveraging its existing Micro LED technology platform and mass production experience. The company aims to build a next generation optoelectronic integration platform for AI computing centers, data centers, and high speed switching architectures, helping the industry address one of the most critical system bottlenecks in the global AI infrastructure competition – enabling high efficiency transmission and scalable interconnection of massive data while power consumption and thermal dissipation pressures continue to rise. Figure 1: Architecture schematic diagram   Three Highlights: Defining the Next Generation Interconnect Standard Aligned with the 800G/1.6T upgrade window: Responding to the bandwidth multiplication and interconnection energy pressures in AI data centers, optical interconnect has become a mandatory requirement for next generation platforms. Direct transferability of Micro LED manufacturable system engineering capabilities: High density I/O, package integration, thermal management, process window control, reliability verification, and test systems match the core challenges of CPO. Deep international collaborative R&D accelerates productization: Co specification, co validation, co design, and long term supply chain alignment establish higher entry barriers and delivery certainty. Industry Background: Copper Electrical Interconnects Reaching Their Limits With "computing power as national strength" and sovereign AI becoming key national strategic priorities, the world is accelerating investment in AI computing infrastructure. Network bandwidth demand is growing almost exponentially, rapidly moving from 400G toward 800G, 1.6T, and beyond. Traditional copper electrical interconnects face insurmountable physical limitations in bandwidth density, transmission distance, power consumption, and heat dissipation, and have become the core bottleneck for system scalability and energy efficiency improvement. As high end GPU single chip power consumption continues to rise, interconnect energy consumption and thermal load issues become even more prominent. Optical interconnect is no longer an option but a fundamental infrastructure requirement.   Figure 2: AI computing center networking architecture (Source: Acta Optica Sinica, 2025, Fig.10)   Architecture Trend: Silicon Photonics + CPO Become the Inevitable Evolution Path The industry widely recognizes Silicon Photonics and CPO as the direction for next generation architecture evolution. By bringing optical engines closer to – or even directly integrating them with – computing/switching chips, CPO can significantly reduce interconnect power loss, thermal load, and system complexity, while improving bandwidth density and overall energy efficiency.   Erised’s Strategy: Entering CPO with "Manufacturable System Engineering" to Shorten Time to Market and Enhance Delivery Certainty The capabilities Erised has accumulated over the long term in the Micro LED field are not limited to chip design, but also encompass "manufacturable system engineering" – including high density I/O, package integration, thermal management, process window control, reliability verification, and test system development. These capabilities heavily overlap with the key challenges of CPO, enabling Erised to transfer its existing methodologies to high speed optical interconnect architectures, shorten the cycle from engineering samples to commercial adoption, and improve delivery certainty. Erised Semiconductor stated: "We adhere to the core principle of 'verifiable, manufacturable, and deliverable' in our CPO strategy. Through system level integration and global partner collaboration, we aim to accelerate the productization and deployment of the next generation high speed optoelectronic integration platform, building long term competitiveness."   System Level Platform Layout: Full Coverage of Electronic ICs, Photonic ICs, 3D Packaging, CPO Architecture, and Thermal Management On the technology roadmap, Erised Semiconductor adopts a system level silicon photonics approach, comprehensively covering electronic ICs, photonic ICs, advanced 3D packaging, CPO architecture, and thermal management technologies. With a highly integrated platform, it provides a sustainable and scalable technology roadmap: capable of supporting current multi terabit data transmission needs, while also evolving to future scales of over hundreds of terabits per second, corresponding to the long cycle, deep level structural transformations of AI infrastructure. Figure 3: System level platform layout of EIC, PIC, and 3D packaging (Source: ASE official blog)   Ecosystem Collaboration: Co spec / Co validation / Co design, and L