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Erised
2026-09-22

Erised Semiconductor Chairman Aliex Chen Wins the "Best Science and Technology Innovation Award" at the 7th Guangdong-Hong Kong-Macao Greater Bay Area Outstanding Young Entrepreneurs Awards

On September 21, the award ceremony of the 7th Guangdong-Hong Kong-Macao Greater Bay Area Outstanding Young Entrepreneurs Awards was grandly held at the Hong Kong Convention and Exhibition Centre. In recognition of his continuous technological breakthroughs and industrialization innovation achievements in the integrated circuit sector, Aliex Chen, Chairman of Erised Semiconductor (Shenzhen) Co., Ltd., was honored with the "Best Science and Technology Innovation Award" at the Guangdong-Hong Kong-Macao Greater Bay Area Outstanding Young Entrepreneurs Awards.  Organized by the Guangdong-Hong Kong-Macao Greater Bay Area Entrepreneurs Alliance, this edition of the selection was open to applications from young entrepreneurs across Guangdong, Hong Kong and Macao, attracting applications from more than 1,000 entrepreneurs. The jury was composed of experts from universities and leading media organizations across Guangdong, Hong Kong and Macao. After multiple rounds of qualification review, technical assessment and comprehensive evaluation, 95 young entrepreneurs were ultimately selected as award winners, covering multiple sectors including science and technology innovation, advanced manufacturing, cultural and creative industries, and big health. John Lee Ka-chiu, Chief Executive of the Hong Kong Special Administrative Region, Zhang Guozhi, Vice Governor of Guangdong Province, and Ng Wai Han, Secretary for Economy and Finance of the Macao Special Administrative Region Government, delivered video addresses. They encouraged young entrepreneurs to seize development opportunities in the Greater Bay Area, devote themselves to science and technology innovation industries, and realize their personal value while integrating into the country's overall development. Distinguished guests including Choi Koon-shum, Chairman of the Guangdong-Hong Kong-Macao Greater Bay Area Entrepreneurs Alliance, and Algernon Yau Ying-wah, Secretary for Commerce and Economic Development of the Hong Kong SAR Government, attended the grand event. As the founder and chairman of Erised Semiconductor, Aliex Chen has long been rooted in Shenzhen and focused on analogue and power integrated circuits. He leads his team to focus on independent R&D and domestic localization of display driver chips and power management chips. The team is also making forward-looking arrangements for R&D in CPO (co-packaged optics) technology to build a key next-generation optoelectronic integration platform for AI computing centers. Its products are widely used in consumer electronics, new energy and other fields. Under his leadership, Erised Semiconductor continues to increase R&D investment, continuously improve its intellectual property system, participate in the formulation of national standards, and promote collaborative innovation among industry, universities and research institutes. It has built a joint laboratory together with the Department of Electronic and Electrical Engineering of Southern University of Science and Technology, helping shore up weak links and promote upgrading of the domestic semiconductor industrial chain. According to Aliex Chen, this honor represents the organizing committee's recognition of Erised Semiconductor's technological innovation achievements and also serves as encouragement for young semiconductor entrepreneurs in the Greater Bay Area. Boasting a complete electronic information industrial chain and abundant talent resources, the Guangdong-Hong Kong-Macao Greater Bay Area serves as fertile ground for the innovative growth of hard-tech enterprises. Going forward, Erised Semiconductor will continue to be rooted in Shenzhen and the Greater Bay Area, keep tackling core chip technologies, uphold independent innovation, actively connect science and technology innovation resources across Guangdong, Hong Kong and Macao, and advance the R&D and implementation of cutting-edge technologies such as CPO. It will empower the development of new quality productive forces through chip technologies and contribute the strength of young sci-tech innovators to the high-quality development of the integrated circuit industry in the Greater Bay Area.
Shenzhen
2026-09-18

Shenzhen TV News Highlights Foreign Trade Growth | Erised Semiconductor Empowers Shenzhen’s Smart Manufacturing with Chips

  ▲ Click to play the video. Recently, Shenzhen TV’s Shenzhen News aired a special report: In the first eight months of this year, Shenzhen’s exports of automatic data processing equipment and its components rose by 26.03% year-on-year. This robust foreign trade figure reflects the continuous optimization of Shenzhen’s foreign trade structure and steady gains in the technological content and global competitiveness of its electronic information industry. As a representative IC design enterprise in Shenzhen, Erised Semiconductor was interviewed for this report. Automatic data processing equipment covers end products such as computers and servers. The growth in its exports relies on underlying support from core chips. From display driver chips and power management chips to high-speed interconnect chips for AI data centers, semiconductors serve as the “heart” and “brain” of complete equipment. They are also key to upgrading exported products toward high-end and intelligent applications. In the interview, Erised Semiconductor stated that Shenzhen boasts China’s complete electronic information industrial cluster, coupled with strong foreign trade export advantages, creating fertile market ground for local IC design firms. The rapid export growth of automatic data processing equipment and components in the first eight months reflects strong global demand for high-performance computing and smart terminals. Meanwhile, it continues to drive order growth and technological iteration in the upstream chip design sector, bringing development opportunities for domestic chip enterprises. Rooted in Shenzhen Qianhai, Erised Semiconductor is a national high-tech enterprise and a Specialized, Refined, Differential and Innovative “Little Giant” enterprise. It focuses on the R&D and design of display driver chips and power management chips. The company’s core team comes from world-leading semiconductor firms. Its domestic market share of flat-panel display driver chips has ranked second for three consecutive years. The company has also made forward-looking layout in the high-speed interconnect track for AI data centers. Its products serve diverse scenarios including industry, automotive electronics, consumer electronics and smart homes, with cumulative chip shipments exceeding 100 million pieces. The impressive performance of Shenzhen’s mechanical and electrical foreign trade has further strengthened Erised Semiconductor’s confidence to develop based in Shenzhen and target global markets. Going forward, Erised Semiconductor will continue to increase R&D investment, uphold independent innovation in hard technologies, closely align with the development needs of Shenzhen’s electronic information industrial cluster, and continuously refine domestic chip solutions. It will contribute chip power to the high-quality development of Shenzhen’s foreign trade and the independent controllability of the semiconductor industrial chain.  
Good
2026-09-11

Good News | Erised Semiconductor Wins the "2026 Hardcore Domestic Substitution Benchmark Award"

On September 10, the 8th Hardcore Chip Ecosystem Conference & Award Ceremony was held at Hall 14, Shenzhen World Exhibition & Convention Center. At the event, Erised Semiconductor (Shenzhen) Co., Ltd. stood out in the 2026 Hardcore Chip Selection for its outstanding achievements in chip R&D, market deployment and domestic chip substitution, and was officially awarded the "2026 Hardcore Domestic Substitution Benchmark Award". Initiated by ChipSage, the award is determined through online voting by hundreds of thousands of engineers and comprehensive evaluation by hundreds of industry experts. It is a prestigious industrial honor in China’s semiconductor sector. Centered on hot topics including edge AI chips, computing power innovation and automotive chips, this year’s conference hosted multiple thematic forums, bringing together industrial chain enterprises, technical specialists and industrial investors to jointly analyze opportunities and challenges within the semiconductor industry. As a core segment of the conference, the Hardcore Chip Selection recognizes IC enterprises in China with remarkable accomplishments in technological innovation, domestic substitution and product commercialization. Winning the "Hardcore Domestic Substitution Benchmark Award" represents dual recognition from industry engineers and expert judges of Erised Semiconductor’s long-term technical investment and industrial practice. Since its establishment, Erised Semiconductor has been rooted in local market demands, committed to independent R&D of core technologies. The company focuses on optimizing chip performance and reliability verification, continuously addressing practical pain points in industrial applications, steadily advancing the localized rollout of key products, and contributing to the independent controllability of the industrial chain. Faced with the rapidly evolving semiconductor market, Erised Semiconductor continues to deepen its technical research. Guided by market needs to refine products, the company connects R&D with real-world application deployment, and keeps expanding the application scope of domestic chips. This award validates the company’s solid accumulation in the domestic substitution track. A representative from Erised Semiconductor stated: “This honor belongs to our team, and it also serves as motivation from the industry. The development of domestic chips is a long journey, yet progress will be made with persistent efforts. Moving forward, Erised Semiconductor will continue to increase R&D investment, develop high-performance chips, deepen collaboration with upstream and downstream partners, stay committed to the mission of domestic substitution, and work alongside industry partners to drive high-quality development of China’s semiconductor industry.  
New
2026-09-09

New Product | Erised Semiconductor ERB2350/1 Series: 2–5 Cell Li-ion Secondary Protection IC

Erised Semiconductor introduces another new addition to its lithium ion BMS protection portfolio — the ERB2350/1 Series of 2  to 5 cell secondary protection ICs. Following the launch of the ERB2140C/D Series 3  to 4 cell primary protection ICs on September 4, Erised Semiconductor further strengthens its lithium battery safety protection product matrix. The ERB2350/1 serves as an independent hardware secondary safety barrier beyond the BMS primary protection, effectively eliminating safety hazards such as overcharge and sense line disconnection in multi cell Li-ion packs. Targeting applications including power tools, notebook battery packs, UPS backup power supplies, and light electric vehicles, it provides a highly reliable hardware safety compliance solution. As the energy density of Li ion equipment continues to rise, relying solely on the primary protection chip still leaves the risk of overcharge induced fire due to device failure. Hardware secondary protection has become an essential part of high reliability battery systems. The ERB2350/1, as an independent secondary protection device, can quickly cut off the charging path when the primary protection fails, establishing a second line of defence for battery safety. The single chip natively supports 2  to 5 cell Li ion applications, and by cascading two chips with simple BJT level-shifting circuitry, the configuration can be extended up to 20 cell high voltage battery packs, offering both design flexibility and BOM cost advantages.   Key Product Advantages High Accuracy Overcharge Detection The chip achieves a room temperature overcharge detection accuracy of ±25 mV and ±40 mV over the full temperature range. The overcharge voltage threshold covers 3.7 V to 4.6 V, suitable for various cell chemistries such as ternary lithium and lithium polymer. It supports 1s, 2s, 4s, and 6s multiple protection delay configurations and incorporates a 20 ms noise reset filtering mechanism: in the event of transient voltage disturbances, the system automatically resets the protection timer, ensuring rapid response while effectively preventing false triggers caused by voltage spikes, thereby improving system immunity. 4 μA Ultra Low Quiescent Current The typical quiescent current is only 4 μA, with a maximum of 7 μA. Compared to conventional secondary protection solutions on the market, power consumption is reduced by 60% 80%, significantly minimizing self consumption during battery pack storage and transportation. This prevents the protection IC’s quiescent current from draining the cells, fully preserving battery storage capacity, extending shelf life, and improving product shelf life performance. Full Pin Wire Break Detection Built in OWP (open wire protection) continuously monitors the sense line status of each cell. If any cell sense line is detected as open, the chip immediately turns off the charging path, eliminating overcharge risks caused by broken wires and enhancing the operational reliability of the battery pack throughout its lifetime. Flexible Topology and Cascade Expansion The single chip can be configured via pin strapping to support 2S, 3S, 4S, or 5S multi cell applications. Two chips can be cascaded to implement 6  to 10 cell high voltage battery modules without the need for expensive high cell count dedicated protection ICs, reducing BOM SKUs, simplifying inventory management, and balancing performance with overall cost. The chip supports both N  and P channel MOS driving, allowing it to drive high side or low side MOSFETs or blow a protection fuse to disconnect the main charging path. Additionally, it features a built in production line fast test mode that shortens test sequences during mass production, enhancing manufacturing efficiency. Excellent Hardware Reliability The chip withstands up to 36 V and offers robust surge immunity. It is available in MSOP 8L and DFN3×4 8L package options, and supports Active High / Active Low as well as open drain output logic, with customisable parameters to meet specific system requirements. The industrial temperature range spans –40 °C to +85 °C, making it suitable for harsh industrial environments.   Product Delivery and Technical Support The ERB2350/1 is now available in multiple standard part numbers covering different overcharge thresholds, delay times, and output logic options. Customised services for voltage thresholds, delays, and output logic are also offered. As lithium battery safety regulations continue to tighten, hardware secondary backup protection is increasingly becoming a key consideration in battery design. With this release, Erised Semiconductor now offers a complete portfolio comprising both the ERB2140C/D primary protection ICs and the ERB2350/1 secondary protection ICs. Customers may choose the primary protection alone, or adopt a "primary + secondary" dual protection architecture to further enhance battery system safety. Erised Semiconductor provides complete application re
New
2026-09-07

New Product | ERISED ERB2140C/D: High-Integration 3–4 Series Li ion Protection IC with Time-Sharing Balancing

ERISED Semiconductor has officially launched the ERB2140C/D series of highly integrated 3–4 series Li ion / Li polymer battery protection ICs, targeting a wide range of applications including cordless vacuum cleaners, robotic vacuum cleaners, floor washers, electric bicycles, portable energy storage power supplies, and base station backup battery packs. The series integrates high precision voltage detection, independent charge/discharge temperature control, time sharing balancing technology, and ultra low sleep current, delivering a cost effective domestic alternative for lithium battery BMS solutions. With the rapid proliferation of cordless vacuum cleaners, floor washers, electric bicycles, and portable energy storage devices, battery pack designs commonly face two major pain points: first, excessive self consumption during factory shipping and long term storage leads to cell under voltage or even permanent damage; second, insufficient adaptability to high and low temperature environments compromises reliability under extreme operating conditions.   One Chip, Covers Two Major Lithium Battery Chemistries The ERB2140C/D series is specifically optimized to address these pain points. The C version is tailored for NMC / Li polymer, while the D version is tailored for Li FePO₄ / Li polymer – one product family covers two mainstream lithium battery systems, significantly shortening customer development cycles.   Four Core Technical Advantages High Accuracy Dual Chemistry Voltage Detection Overcharge detection accuracy reaches ±25mV at room temperature, and over discharge detection accuracy reaches ±30mV, precisely monitoring each cell voltage to effectively avoid lithium plating due to overcharge and irreversible damage from over discharge. Independent Charge/Discharge Temperature Control Charge and discharge temperature thresholds are independently configured via external NTC and resistors; the two sets of parameters for charge over temperature / low temperature and discharge over temperature / low temperature do not interfere with each other, flexibly adapting to various operating conditions including severe cold and high heat. SEL Pin for Flexible Series Count Switching A simple configuration enables switching between 3 series and 4 series, and the IC can directly drive external N channel charge and discharge MOSFETs without additional driver circuits, significantly reducing BOM cost. Ultra Low Sleep Current Normal operating current at room temperature is 15µA; when cells enter over discharge state, the IC automatically switches to 5µA ultra low sleep mode, effectively solving the problem of cell under voltage damage caused by excessive self consumption during storage and transportation, and extending the shelf life of end products.   Intelligent Alternating Time Sharing Balancing Technology On top of the four core advantages, the ERB2140C/D also features an innovative time sharing balancing technology. The chip uses a 24ms cycle to perform time division switching balancing between channels 1&3 and channels 2&4, fundamentally eliminating the risk of false turn on of MOSFETs in adjacent channels. The built in MOS balancing supports 500Ω~2kΩ, and external transistors can also be added to achieve high current active balancing. Built in 8 second cycle cell disconnection detection; upon abnormal sampling line conditions, the charge/discharge path is immediately cut off. Comprehensive Charge/Discharge Safety Protection Discharge Side Over discharge protection: precisely monitors each cell and immediately turns off DO upon low voltage. Three level overcurrent protection: discharge overcurrent 1, discharge overcurrent 2, and short circuit fast response. Load lock: discharge is locked after overcurrent or over temperature, and automatically recovers upon load removal. Charge Side Overcharge protection delay with reset function, resistant to transient interference. Charge overcurrent protection: detects abnormal current in the charging path and cuts it off in time. Selected models support 0V activation charging, capable of waking up fully self discharged batteries.   Hardware Package and Technical Support The IC is offered in a compact SSOP 16L package, supports an industrial temperature range of -40℃ to +85℃, and achieves ESD protection levels of HBM 4KV / CDM 1KV. ERISED Semiconductor provides 3 series / 4 series common port and separate port reference designs as well as external current expansion balancing solutions, and is backed by a professional FAE team supporting circuit debugging, parameter customization, and production ramp up. For samples, datasheets, or reference designs, please feel free to contact us.   Coming Soon: ER2350/1 Series Secondary Protection ICs
From
2026-08-12

From Electricity to Light, We Redefine "Driving"

Six months ago, when CPO was still on the eve of mass production at scale, we did one thing: we announced our full scale entry into CPO. Half a year later, NVIDIA's Spectrum X CPO switches have started shipping to partners, and Broadcom's 51.2T Bailly CPO switches are maintaining small volume production. CPO has officially moved from proof of concept into the commercial mass production phase. Looking back, that decision was not impulsive. It was not only a strategic choice to align with the generational shift in AI computing infrastructure, but also a critical leap that transforms our deep expertise in display drivers and power management into a core competitive edge in next generation optoelectronic integration. As a company that started with display drivers and power management, our move into CPO is by no means blind diversification; it is grounded in the commonality of underlying technologies: Core Positioning in Power Management: CPO modules integrate optical engines and switching chips with high density, imposing stringent demands on local power supply stability, transient response, and energy efficiency. Our deep accumulation in power management ICs (PMICs) is now being transformed into high density power modules and laser driver chips (LDDs) for CPO optical engines, delivering customized, high precision, low noise power solutions. Synergy of Precision Driving: Our accumulated expertise in precision signal control and packaging processes from display drivers aligns exceptionally well with the precision driving requirements for lasers and modulators in CPO optical engines. This capability is now extending to critical components on the receiving end, such as trans impedance amplifiers (TIAs) and optical modulator driver chips, covering the entire optical signal transmission and reception chain. Embracing Next Generation Technology Evolution: In addition to the mainstream silicon photonics route, we are also actively evaluating emerging technology paths such as Micro LED optical communication. These new technologies pose entirely fresh demands on driving and power, which are precisely the ideal battleground for us to leverage our dual genetic strengths in display drivers and power management. The year 2026 marks the first year of CPO mass production and also our starting year on the optoelectronic integration track. Leveraging our core technological accumulations in Micro LED device driving, optoelectronic calibration, and mass transfer defect compensation, we are extending our dual genetic advantages in display drivers and power management into the field of Micro LED high speed optical interconnects for AI data centers. To date, the company has accumulated over 70 patents, shipped more than 200 million chips in total, and served over 100 clients worldwide. Behind these numbers lies our complete capability loop from R&D to mass production, from validation to delivery, in display drivers and power management. It is precisely this capability that emboldened us to make the strategic decision to fully enter CPO when it was still on the eve of large scale mass production. Looking ahead, we will continue to uphold our core principle of "verifiable, mass producible, and deliverable," striving for excellence in our foundational businesses of power and driving. We will keep increasing R&D investment, collaborate with upstream and downstream partners across the industrial chain, and jointly build a prosperous and healthy semiconductor ecosystem, contributing unique value to the CPO ecosystem. From screens to optical engines, from Micro LED to CPO—we are already on board the vast ocean of optoelectronic integration.   Media Contact: Tel: 0755-26671807 Sales Email: sales@erised-semi.com Website: www.erised-semi.com    
From
2026-08-05

From Micro LED to CPO: Erised Semiconductor Builds a Next Generation Key Platform for Optoelectronic Integration

Targeting the 800G/1.6T upgrade wave, accelerating the deployment of optical interconnects in AI computing centers with "verifiable, manufacturable, and deliverable" solutions. Erised Semiconductor today announced that it will officially enter the CPO (Co Packaged Optics) field, leveraging its existing Micro LED technology platform and mass production experience. The company aims to build a next generation optoelectronic integration platform for AI computing centers, data centers, and high speed switching architectures, helping the industry address one of the most critical system bottlenecks in the global AI infrastructure competition – enabling high efficiency transmission and scalable interconnection of massive data while power consumption and thermal dissipation pressures continue to rise. Figure 1: Architecture schematic diagram   Three Highlights: Defining the Next Generation Interconnect Standard Aligned with the 800G/1.6T upgrade window: Responding to the bandwidth multiplication and interconnection energy pressures in AI data centers, optical interconnect has become a mandatory requirement for next generation platforms. Direct transferability of Micro LED manufacturable system engineering capabilities: High density I/O, package integration, thermal management, process window control, reliability verification, and test systems match the core challenges of CPO. Deep international collaborative R&D accelerates productization: Co specification, co validation, co design, and long term supply chain alignment establish higher entry barriers and delivery certainty. Industry Background: Copper Electrical Interconnects Reaching Their Limits With "computing power as national strength" and sovereign AI becoming key national strategic priorities, the world is accelerating investment in AI computing infrastructure. Network bandwidth demand is growing almost exponentially, rapidly moving from 400G toward 800G, 1.6T, and beyond. Traditional copper electrical interconnects face insurmountable physical limitations in bandwidth density, transmission distance, power consumption, and heat dissipation, and have become the core bottleneck for system scalability and energy efficiency improvement. As high end GPU single chip power consumption continues to rise, interconnect energy consumption and thermal load issues become even more prominent. Optical interconnect is no longer an option but a fundamental infrastructure requirement.   Figure 2: AI computing center networking architecture (Source: Acta Optica Sinica, 2025, Fig.10)   Architecture Trend: Silicon Photonics + CPO Become the Inevitable Evolution Path The industry widely recognizes Silicon Photonics and CPO as the direction for next generation architecture evolution. By bringing optical engines closer to – or even directly integrating them with – computing/switching chips, CPO can significantly reduce interconnect power loss, thermal load, and system complexity, while improving bandwidth density and overall energy efficiency.   Erised’s Strategy: Entering CPO with "Manufacturable System Engineering" to Shorten Time to Market and Enhance Delivery Certainty The capabilities Erised has accumulated over the long term in the Micro LED field are not limited to chip design, but also encompass "manufacturable system engineering" – including high density I/O, package integration, thermal management, process window control, reliability verification, and test system development. These capabilities heavily overlap with the key challenges of CPO, enabling Erised to transfer its existing methodologies to high speed optical interconnect architectures, shorten the cycle from engineering samples to commercial adoption, and improve delivery certainty. Erised Semiconductor stated: "We adhere to the core principle of 'verifiable, manufacturable, and deliverable' in our CPO strategy. Through system level integration and global partner collaboration, we aim to accelerate the productization and deployment of the next generation high speed optoelectronic integration platform, building long term competitiveness."   System Level Platform Layout: Full Coverage of Electronic ICs, Photonic ICs, 3D Packaging, CPO Architecture, and Thermal Management On the technology roadmap, Erised Semiconductor adopts a system level silicon photonics approach, comprehensively covering electronic ICs, photonic ICs, advanced 3D packaging, CPO architecture, and thermal management technologies. With a highly integrated platform, it provides a sustainable and scalable technology roadmap: capable of supporting current multi terabit data transmission needs, while also evolving to future scales of over hundreds of terabits per second, corresponding to the long cycle, deep level structural transformations of AI infrastructure. Figure 3: System level platform layout of EIC, PIC, and 3D packaging (Source: ASE official blog)   Ecosystem Collaboration: Co spec / Co validation / Co design, and L
Erised
2026-08-05

Erised Semiconductor's "Key Technologies for AMOLED Display Driver Chips" passed the scientific and technological achievement registration with the Ministry of Industry and Information Technology

On June 24, 2026, Erised Semiconductor (Shenzhen) Co., Ltd. completed the registration of scientific and technological achievements with the Ministry of Industry and Information Technology (MIIT) for its Research and Application of Key Technologies for AMOLED Display Driver Chips, with registration certificate No. 3392026Y0668. The registration authority was the China Academy of Information and Communications Technology (CAICT). On the same day, the joint laboratory of Erised Semiconductor and the Department of Electronic and Electrical Engineering at Southern University of Science and Technology (SUSTech) was inaugurated in Shenzhen, marking another step in industry university research collaborative innovation. These two milestones falling on the same day signify that this semiconductor enterprise rooted in Qianhai, Shenzhen, has gained nationally recognized authority for its technological strength in AMOLED display driver chips.   Seven Years of Deep Cultivation: From Chasing to Running Side by Side Founded in August 2018 and headquartered in the Qianhai Shenzhen Hong Kong Cooperation Zone, Erised Semiconductor is a national high tech enterprise. The company focuses on the R&D and sales of display driver chips, power management chips, and motor driver chips. Its core team comes from leading international semiconductor companies and holds dozens of domestic patents. In the display driver field, Erised has achieved a complete domestic product line layout. Its panel partners include industry leaders such as BOE and Truly, and its end products are supplied to well known domestic and international brands including TCL and Amazon. From TFT LCD to AMOLED and even Micro LED, Erised’s product portfolio covers the full spectrum of display technologies. The Key Technologies for AMOLED Display Driver Chips, which received this scientific and technological achievement registration, embodies the company’s years of R&D investment in this field. In March 2021, the AMOLED driver chip ER76288 for wearable applications entered mass production. In March 2024, Erised launched a new generation AMOLED driver chip for smartphones, ER66638, which adopts self developed display related algorithms including Demura, IRC, CTC, and other core technologies, effectively improving display quality and yield while reducing power consumption and cost. This IC flexibly switches functions in SRAM usage and is the smallest form factor solution in the industry that supports command mode, enabling seamless integration with different APs and panel manufacturers. In October 2025, it released the ER75138 – an AMOLED driver chip for smart bands and e cigarettes – further advancing the domestic substitution process in this field.   A Key Piece in the Domestic Substitution Puzzle AMOLED display technology, with its advantages of ultra thinness, high brightness, low power consumption, and high contrast, has become the preferred display solution for mobile devices such as smartphones, tablets, and smartwatches. The share of AMOLED in global mobile phone sales has already exceeded half and is expected to surpass 60% by 2026. Sales of AMOLED display driver chips in mainland China grew from 180 million units in 2020 to 478 million units in 2024, with a compound annual growth rate of 27.6%, and the global share rose from 24.9% to 37.0%. However, in this rapidly growing market, AMOLED driver ICs have long been dominated by overseas suppliers such as Samsung and Novatek, with insufficient support for refurbished and renewed market devices. Erised’s AMOLED driver chips were born precisely to fill this market gap. To date, they have been validated by several leading panel manufacturers on displays ranging from 0.74 to 6.9 inches and have already entered mass production and shipment. Passing the MIIT scientific and technological achievement registration means that the advancement, maturity, and application value of this technology have been officially confirmed at the national level. The registration is not only an important supporting document for national management of scientific achievements and recommendation for science and technology awards, but also helps gain recognition from investors and partners, serving as a key criterion for evaluating the value of the achievement.   Integrating Industry, Academia, and Research to Deploy Next Generation Display Technologies On the same day as the achievement registration, the joint laboratory of Erised Semiconductor and the Department of Electronic and Electrical Engineering at SUSTech was officially inaugurated. Leveraging Erised’s production platform and SUSTech’s research strengths, the joint laboratory will be built into an innovation platform that integrates research facility construction, industrial technology R&D and integration, talent cultivation, application demonstrations, and commercialization of results. At the unveiling ceremony, Erised’s chairman, Aliex, stated that the domestic semico
CPO
2026-08-04

CPO Moves from Concept to Mass Production, Ushering in a New Era of Optical Interconnection

"When glass substrates meet optical engines, and precision power management enables silicon photonic chips—in 2026, we officially announce our entry into CPO. This is not just an expansion of our business territory, but a strategic convergence rooted in common underlying technologies." Historic Inflection Point: CPO Moves from Concept to Mass Production In July 2026, the optical communications industry finally heard the long-awaited "starting gun." NVIDIA began shipping its next-generation Spectrum-X CPO switches to select partners, while Broadcom's 51.2T Bailly CPO switches continued small volume production—Co Packaged Optics (CPO) technology has officially transitioned from laboratory verification to commercial mass production. This is not only a victory for the technical roadmap, but also heralds the start of an entirely new industry cycle.   What is CPO and Why Does It Become an Industry Focus? In essence, CPO moves the optical module (optical engine) from the outer face of the switch into its heart, packaging it together with the ASIC switching chip. The optical engine, optical chips, and switching ASIC are all packaged on the same substrate, reducing the optical electrical interconnection distance to less than 1 cm and achieving industry best signal loss levels. Compared with traditional pluggable optical modules, CPO offers outstanding advantages. In conventional solutions, electrical signals must travel long distances across the circuit board, and as speeds exceed 1.6 Tbps they approach physical limits. CPO shortens the electrical signal transmission distance from centimeters to millimeters, dramatically reducing power consumption and latency. For example, Broadcom's 51.2T Bailly CPO switch reduces power consumption by about 70% compared with traditional pluggable optical modules. Schematic diagram of Co Packaged Optics (CPO) technology (Image source: Sina Finance)   Two Flagship Products Land, Ushering in the Mass Production  The two current landmark CPO products have both entered mass production: NVIDIA Spectrum X CPO switch, developed by NVIDIA in collaboration with TSMC using the COUPE advanced packaging process, delivers a total switching capacity of 400 Tb/s, with production capacity expected to expand further in the second half of 2026. Broadcom 51.2T Bailly CPO switch, brought to mass production with assistance from Delta Electronics and Micas Networks, has completed deployment verification by hyperscale cloud providers such as Meta, with preliminary confirmation of feasibility in real world data center environments. The successive launch of these two flagship products marks the formal transition of CPO from technology validation to scaled commercialization. NVIDIA Spectrum X CPO Switch (Image source: Apple Daily News)   Market Outlook: A Multi Billion Dollar Blue Ocean Accelerates Several authoritative institutions have issued highly optimistic forecasts for the CPO market: Yole Group's July 2026 report "Data Center Co packaged Optics 2026" states that CPO has moved from concept to commercial reality, with development speed and scale far exceeding 2023 expectations. Global CPO optical engine revenue will grow at a CAGR of approximately 228% from 2026 to 2031, reaching US$112 billion by 2031. Light Counting projects that the AI driven optical transceiver and CPO market will reach US$16.5 billion in 2025 and surge to US$26 billion in 2026, an annual growth rate of 60%. Trend Force forecasts that CPO penetration will rise from about 0.55% in 2026 to about 8% in 2028, corresponding to a market size of approximately US$3.3 billion. Other data show that the global CPO market will reach US$2 billion in 2026, up more than 400% year on year; the Chinese market will exceed RMB 10 billion, with growth surpassing 500%. Goldman Sachs, in its latest research report, raised its forecast for the global optical module market, projecting US$50.9 billion in 2026 and US$72.6 billion in 2027. The Yole report specifically notes that Scale Up is the "killer application" for CPO—copper interconnects have reached physical limits under the trend of doubling bandwidth, making CPO the only viable path to achieving larger scale GPU clusters. Scale Up switch optical engines and compute optical engines together account for about 94% of the market, representing the largest revenue source. Image source: Yole Group, "Data Center Co packaged Optics 2026"   Three Major Bottlenecks: Mass Production Is Only the Beginning Mass production does not mean supply bottlenecks are eliminated. TrendForce notes that the CPO switch supply chain faces three core constraints: First, the optical engine segment. Optical engines require the integration of lasers, modulators, and many other components, with complex processes and extremely high yield requirements, compounded by thermal management challenges. Only a few suppliers currently have mass‑production capabilities. Second, silicon photonics capac
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Erised Semiconductor Chairman Aliex Chen Wins the "Best Science and Technology Innovation Award" at the 7th Guangdong-Hong Kong-Macao Greater Bay Area Outstanding Young Entrepreneurs Awards News 丨 2026-09-22 丨
On September 21, the award ceremony of the 7th Guangdong-Hong Kong-Macao Greater Bay Area Outstanding Young Entrepreneurs Awards was grandly held at the Hong Kong Convention and Exhibition Centre. In recognition of his continuous technological breakthroughs and industrialization innovation achievements in the integrated circuit sector, Aliex Chen, Chairman of Erised Semiconductor (Shenzhen) Co., Ltd., was honored with the "Best Science and Technology Innovation Award" at the Guangdong-Hong Kong-Macao Greater Bay Area Outstanding Young Entrepreneurs Awards.  Organized by the Guangdong-Hong Kong-Macao Greater Bay Area Entrepreneurs Alliance, this edition of the selection was open to applications from young entrepreneurs across Guangdong, Hong Kong and Macao, attracting applications from more than 1,000 entrepreneurs. The jury was composed of experts from universities and leading media organizations across Guangdong, Hong Kong and Macao. After multiple rounds of qualification review, technical assessment and comprehensive evaluation, 95 young entrepreneurs were ultimately selected as award winners, covering multiple sectors including science and technology innovation, advanced manufacturing, cultural and creative industries, and big health. John Lee Ka-chiu, Chief Executive of the Hong Kong Special Administrative Region, Zhang Guozhi, Vice Governor of Guangdong Province, and Ng Wai Han, Secretary for Economy and Finance of the Macao Special Administrative Region Government, delivered video addresses. They encouraged young entrepreneurs to seize development opportunities in the Greater Bay Area, devote themselves to science and technology innovation industries, and realize their personal value while integrating into the country's overall development. Distinguished guests including Choi Koon-shum, Chairman of the Guangdong-Hong Kong-Macao Greater Bay Area Entrepreneurs Alliance, and Algernon Yau Ying-wah, Secretary for Commerce and Economic Development of the Hong Kong SAR Government, attended the grand event. As the founder and chairman of Erised Semiconductor, Aliex Chen has long been rooted in Shenzhen and focused on analogue and power integrated circuits. He leads his team to focus on independent R&D and domestic localization of display driver chips and power management chips. The team is also making forward-looking arrangements for R&D in CPO (co-packaged optics) technology to build a key next-generation optoelectronic integration platform for AI computing centers. Its products are widely used in consumer electronics, new energy and other fields. Under his leadership, Erised Semiconductor continues to increase R&D investment, continuously improve its intellectual property system, participate in the formulation of national standards, and promote collaborative innovation among industry, universities and research institutes. It has built a joint laboratory together with the Department of Electronic and Electrical Engineering of Southern University of Science and Technology, helping shore up weak links and promote upgrading of the domestic semiconductor industrial chain. According to Aliex Chen, this honor represents the organizing committee's recognition of Erised Semiconductor's technological innovation achievements and also serves as encouragement for young semiconductor entrepreneurs in the Greater Bay Area. Boasting a complete electronic information industrial chain and abundant talent resources, the Guangdong-Hong Kong-Macao Greater Bay Area serves as fertile ground for the innovative growth of hard-tech enterprises. Going forward, Erised Semiconductor will continue to be rooted in Shenzhen and the Greater Bay Area, keep tackling core chip technologies, uphold independent innovation, actively connect science and technology innovation resources across Guangdong, Hong Kong and Macao, and advance the R&D and implementation of cutting-edge technologies such as CPO. It will empower the development of new quality productive forces through chip technologies and contribute the strength of young sci-tech innovators to the high-quality development of the integrated circuit industry in the Greater Bay Area.

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