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CPO
2026-08-04

CPO Moves from Concept to Mass Production, Ushering in a New Era of Optical Interconnection

"When glass substrates meet optical engines, and precision power management enables silicon photonic chips—in 2026, we officially announce our entry into CPO. This is not just an expansion of our business territory, but a strategic convergence rooted in common underlying technologies." Historic Inflection Point: CPO Moves from Concept to Mass Production In July 2026, the optical communications industry finally heard the long-awaited "starting gun." NVIDIA began shipping its next-generation Spectrum-X CPO switches to select partners, while Broadcom's 51.2T Bailly CPO switches continued small volume production—Co Packaged Optics (CPO) technology has officially transitioned from laboratory verification to commercial mass production. This is not only a victory for the technical roadmap, but also heralds the start of an entirely new industry cycle.   What is CPO and Why Does It Become an Industry Focus? In essence, CPO moves the optical module (optical engine) from the outer face of the switch into its heart, packaging it together with the ASIC switching chip. The optical engine, optical chips, and switching ASIC are all packaged on the same substrate, reducing the optical electrical interconnection distance to less than 1 cm and achieving industry best signal loss levels. Compared with traditional pluggable optical modules, CPO offers outstanding advantages. In conventional solutions, electrical signals must travel long distances across the circuit board, and as speeds exceed 1.6 Tbps they approach physical limits. CPO shortens the electrical signal transmission distance from centimeters to millimeters, dramatically reducing power consumption and latency. For example, Broadcom's 51.2T Bailly CPO switch reduces power consumption by about 70% compared with traditional pluggable optical modules. Schematic diagram of Co Packaged Optics (CPO) technology (Image source: Sina Finance)   Two Flagship Products Land, Ushering in the Mass Production  The two current landmark CPO products have both entered mass production: NVIDIA Spectrum X CPO switch, developed by NVIDIA in collaboration with TSMC using the COUPE advanced packaging process, delivers a total switching capacity of 400 Tb/s, with production capacity expected to expand further in the second half of 2026. Broadcom 51.2T Bailly CPO switch, brought to mass production with assistance from Delta Electronics and Micas Networks, has completed deployment verification by hyperscale cloud providers such as Meta, with preliminary confirmation of feasibility in real world data center environments. The successive launch of these two flagship products marks the formal transition of CPO from technology validation to scaled commercialization. NVIDIA Spectrum X CPO Switch (Image source: Apple Daily News)   Market Outlook: A Multi Billion Dollar Blue Ocean Accelerates Several authoritative institutions have issued highly optimistic forecasts for the CPO market: Yole Group's July 2026 report "Data Center Co packaged Optics 2026" states that CPO has moved from concept to commercial reality, with development speed and scale far exceeding 2023 expectations. Global CPO optical engine revenue will grow at a CAGR of approximately 228% from 2026 to 2031, reaching US$112 billion by 2031. Light Counting projects that the AI driven optical transceiver and CPO market will reach US$16.5 billion in 2025 and surge to US$26 billion in 2026, an annual growth rate of 60%. Trend Force forecasts that CPO penetration will rise from about 0.55% in 2026 to about 8% in 2028, corresponding to a market size of approximately US$3.3 billion. Other data show that the global CPO market will reach US$2 billion in 2026, up more than 400% year on year; the Chinese market will exceed RMB 10 billion, with growth surpassing 500%. Goldman Sachs, in its latest research report, raised its forecast for the global optical module market, projecting US$50.9 billion in 2026 and US$72.6 billion in 2027. The Yole report specifically notes that Scale Up is the "killer application" for CPO—copper interconnects have reached physical limits under the trend of doubling bandwidth, making CPO the only viable path to achieving larger scale GPU clusters. Scale Up switch optical engines and compute optical engines together account for about 94% of the market, representing the largest revenue source. Image source: Yole Group, "Data Center Co packaged Optics 2026"   Three Major Bottlenecks: Mass Production Is Only the Beginning Mass production does not mean supply bottlenecks are eliminated. TrendForce notes that the CPO switch supply chain faces three core constraints: First, the optical engine segment. Optical engines require the integration of lasers, modulators, and many other components, with complex processes and extremely high yield requirements, compounded by thermal management challenges. Only a few suppliers currently have mass‑production capabilities. Second, silicon photonics capac
Erised
2026-06-29

Erised – SUSTech Department of Electronic and Electrical Engineering Joint Laboratory Inaugurated

On the morning of June 24, 2026, Erised (Shenzhen) Co., Ltd. and the Department of Electronic and Electrical Engineering at Southern University of Science and Technology (SUSTech) jointly inaugurated the “SUSTech Department of Electronic and Electrical Engineering – Erised Joint Laboratory” in Conference Room 812 of the College of Engineering.  Attending the ceremony were Erised’s Chairman Chen Tingyang, General Manager of the Display Driver Business Group Xie Yuxuan, and other core members of the company. From SUSTech, Professor Chen Mingwei, Dean of the College of Engineering, Associate Professors Jiang Junmin and Hua Mengyuan, Research Assistant Professor Hu Chen from the Department of Electronic and Electrical Engineering, as well as Associate Professor Gao Yuan from the School of Microelectronics, along with faculty and student representatives, gathered to witness this important moment.   At the start of the unveiling ceremony, Professor Chen Mingwei, Dean of SUSTech’s College of Engineering, delivered the first address and extended a warm welcome to Chairman Chen Tingyang and his delegation. He noted that the College of Engineering has developed rapidly in the field of information semiconductors, thanks to university industry collaboration and support from the Shenzhen municipal government. In recent years, the College has performed exceptionally well in research funding, with nearly one third of its annual research budget coming from the semiconductor and information industries. He emphasized that the semiconductor industry is currently experiencing an AI driven super cycle expansion, with an upward trend spanning the entire industrial chain—from chips, memory, and optoelectronics to AI automation. This technological boom provides a strategic window for enterprise university cooperation. The College will support the joint laboratory in terms of policy and value creation, and hopes that both sides will build a mutually beneficial mechanism for integrating production, education, research, and application. Through collaborative research, they aim to solve key technological issues in emerging industries, actively encourage students to undertake internships and practical training in the company, and cultivate students’ practical innovation capabilities through teaching cooperation. [Speech by Dean Chen Mingwei] Chairman Chen Tingyang shared Erised’s growth journey in his speech. Over the past seven years, Erised has been deeply engaged in the chip sector, focusing on R&D in display drivers, power management, and optical interconnect ICs. The company’s core R&D team comes from leading semiconductor companies in the industry, possessing solid know how in industrialization. He remarked that China’s semiconductor industry stands at a critical turning point from technology introduction to independent innovation, and that the deep coupling of industrial upgrade demands with university research strengths will be a key path to breaking through core technology bottlenecks. Erised has long valued university industry partnerships, and the company is full of anticipation for this collaboration with SUSTech. In the future, the joint laboratory will serve as an important vehicle to fully integrate the company’s industrial platform with the university’s research resources, deeply connecting the entire chain of production, education, research, and application, so that both parties can complement each other’s strengths and achieve mutual progress. [Speech by Chairman Chen Tingyang] Mr. Xie Yuxuan, General Manager of the Display Driver Business Group, gave a comprehensive presentation on Erised’s overall development strategy and core product lines to the university leaders, faculty, and students. He explained that the company currently focuses on two major chip tracks: display drivers and power management. In the display driver field, Erised has completed the full deployment of a domestic product line, which constitutes its differentiated core competitiveness. Its panel partners include industry leaders such as BOE and Truly, and its end products supply well known domestic and international brands including TCL and Amazon. The power management business has also undergone a strategic upgrade, combining sustained independent R&D with expanded industrial investment, and collaborating with multiple partners to jointly develop power ICs for small electric devices. He expressed the hope that, through the newly established joint laboratory, the company can engage in deeper, more targeted collaborative research with the SUSTech team。 [Speech by General Manager Xie Yuxuan] Subsequently, Chairman Chen Tingyang and Dean Chen Mingwei jointly unveiled the plaque for the joint laboratory. [Unveiling ceremony]  Following the unveiling, Associate Professor Jiang Junmin from SUSTech’s Department of Electronic and Electrical Engineering, who serves as the Director of the joint laboratory, presented the 2026 2027 construc
Honor
2026-05-09

Honor Crowned! Erised Semiconductor Wins "Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industry Pilot Enterprise" Award

Under the theme "Innovation · Co-construction of the Chain", the NEX WAVE 2026 Greater Bay Area Strategic Emerging Industries and Future Industries Ecosystem Connectivity Conference was recently held with great ceremony in Shenzhen. The conference was co-hosted by the Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industries Development Promotion Association and the Shenzhen Strategic Emerging Industries Development Promotion Association. More than 500 elites from government, industry, academia, research, finance and other fields gathered to discuss the development of new quality productive forces and industrial ecosystem collaboration. At the conference, Erised Semiconductor (Shenzhen) Co., Ltd., by virtue of its outstanding independent innovation capability and industrial leadership, was awarded the "2025 Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industry Pilot Enterprise" title jointly issued by the Guangdong-Hong Kong-Macao Greater Bay Area Strategic Emerging Industries Development Promotion Association and the Shenzhen Strategic Emerging Industries Development Promotion Association! It is reported that this selection campaign officially opened for registration in May 2025 and lasted a total of 8 months. Through steps including "press release, registration, preliminary material review, on-site research, and expert comprehensive evaluation", comprehensive assessments were made across multiple areas such as scientific research, venture capital, industry, and corporate services. In the end, 50 enterprises were selected for the "Pilot Enterprise" list, of which 56% are national-level "Little Giant" specialized and sophisticated enterprises, holding a total of over 17,000 patents. This research is a comprehensive benchmark project initiated by the Strategic Emerging Industries Development Promotion Association in conjunction with several authoritative institutions. It has been held for five consecutive years, cumulatively releasing 250 pilot enterprises, 48 pioneering figures, and 100 young leaders, forming the most influential benchmark ecosystem for strategic emerging industries in the Greater Bay Area. In such a rigorous and authoritative selection, Erised Semiconductor broke through forcefully and, with its outstanding independent innovation capability and industry leadership, was honored on the "Pilot Enterprise" list, adding yet another authoritative accolade in the field of strategic emerging industries. From High-tech Enterprise to Specialized and Sophisticated "Little Giant", and then to Shenzhen Gazelle Enterprise, and now the Greater Bay Area Strategic Emerging Industry "Pilot Enterprise" — every step of Erised Semiconductor's growth has been inseparable from its persistent dedication to technological innovation, and even more so from the trust and support of every customer, partner, and employee. In the future, we will continue to move forward with this honor, contributing irreplaceable "Erised Power" to the high-quality development of the semiconductor industry in the Greater Bay Area with even stronger innovation!
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Erised – SUSTech Department of Electronic and Electrical Engineering Joint Laboratory Inaugurated News 丨 2026-06-29
On the morning of June 24, 2026, Erised (Shenzhen) Co., Ltd. and the Department of Electronic and Electrical Engineering at Southern University of Science and Technology (SUSTech) jointly inaugurated the “SUSTech Department of Electronic and Electrical Engineering – Erised Joint Laboratory” in Conference Room 812 of the College of Engineering.  Attending the ceremony were Erised’s Chairman Chen Tingyang, General Manager of the Display Driver Business Group Xie Yuxuan, and other core members of the company. From SUSTech, Professor Chen Mingwei, Dean of the College of Engineering, Associate Professors Jiang Junmin and Hua Mengyuan, Research Assistant Professor Hu Chen from the Department of Electronic and Electrical Engineering, as well as Associate Professor Gao Yuan from the School of Microelectronics, along with faculty and student representatives, gathered to witness this important moment.   At the start of the unveiling ceremony, Professor Chen Mingwei, Dean of SUSTech’s College of Engineering, delivered the first address and extended a warm welcome to Chairman Chen Tingyang and his delegation. He noted that the College of Engineering has developed rapidly in the field of information semiconductors, thanks to university industry collaboration and support from the Shenzhen municipal government. In recent years, the College has performed exceptionally well in research funding, with nearly one third of its annual research budget coming from the semiconductor and information industries. He emphasized that the semiconductor industry is currently experiencing an AI driven super cycle expansion, with an upward trend spanning the entire industrial chain—from chips, memory, and optoelectronics to AI automation. This technological boom provides a strategic window for enterprise university cooperation. The College will support the joint laboratory in terms of policy and value creation, and hopes that both sides will build a mutually beneficial mechanism for integrating production, education, research, and application. Through collaborative research, they aim to solve key technological issues in emerging industries, actively encourage students to undertake internships and practical training in the company, and cultivate students’ practical innovation capabilities through teaching cooperation. [Speech by Dean Chen Mingwei] Chairman Chen Tingyang shared Erised’s growth journey in his speech. Over the past seven years, Erised has been deeply engaged in the chip sector, focusing on R&D in display drivers, power management, and optical interconnect ICs. The company’s core R&D team comes from leading semiconductor companies in the industry, possessing solid know how in industrialization. He remarked that China’s semiconductor industry stands at a critical turning point from technology introduction to independent innovation, and that the deep coupling of industrial upgrade demands with university research strengths will be a key path to breaking through core technology bottlenecks. Erised has long valued university industry partnerships, and the company is full of anticipation for this collaboration with SUSTech. In the future, the joint laboratory will serve as an important vehicle to fully integrate the company’s industrial platform with the university’s research resources, deeply connecting the entire chain of production, education, research, and application, so that both parties can complement each other’s strengths and achieve mutual progress. [Speech by Chairman Chen Tingyang] Mr. Xie Yuxuan, General Manager of the Display Driver Business Group, gave a comprehensive presentation on Erised’s overall development strategy and core product lines to the university leaders, faculty, and students. He explained that the company currently focuses on two major chip tracks: display drivers and power management. In the display driver field, Erised has completed the full deployment of a domestic product line, which constitutes its differentiated core competitiveness. Its panel partners include industry leaders such as BOE and Truly, and its end products supply well known domestic and international brands including TCL and Amazon. The power management business has also undergone a strategic upgrade, combining sustained independent R&D with expanded industrial investment, and collaborating with multiple partners to jointly develop power ICs for small electric devices. He expressed the hope that, through the newly established joint laboratory, the company can engage in deeper, more targeted collaborative research with the SUSTech team。 [Speech by General Manager Xie Yuxuan] Subsequently, Chairman Chen Tingyang and Dean Chen Mingwei jointly unveiled the plaque for the joint laboratory. [Unveiling ceremony]  Following the unveiling, Associate Professor Jiang Junmin from SUSTech’s Department of Electronic and Electrical Engineering, who serves as the Director of the joint laboratory, presented the 2026 2027 construc

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